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-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity endian_cpu_0 is 
        port (
              -- inputs:
                 signal dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

              -- outputs:
                 signal result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
              );
end entity endian_cpu_0;


architecture europa of endian_cpu_0 is

begin

  --s1, which is an e_custom_instruction_slave
  result(7 DOWNTO 0) <= dataa(31 DOWNTO 24);
  result(15 DOWNTO 8) <= dataa(23 DOWNTO 16);
  result(23 DOWNTO 16) <= dataa(15 DOWNTO 8);
  result(31 DOWNTO 24) <= dataa(7 DOWNTO 0);

end europa;

